The present application relates to semiconductor device fabrication and, more particularly to a method and a structure that enable preventing electrical shorts of source/drain regions in fin field effect transistors (FinFETs).
FinFET technology promises continued scaling of complementary metal oxide semiconductor (CMOS) technology due to the potential to reduce deleterious short channel effects. In current FinFET-based CMOS fabrication processes, a gate electrode needs to extend beyond the active region to a greater extent than it would otherwise be needed to ensure that a source region and a drain region (collectively referred to as “source/drain” regions) are not merged at ends of the gate electrode which causes electrical shorts of the source/drain regions, especially when source/drain epitaxial growth is used to merge the semiconductor fins. However, the large gate extension leads to area penalty as well as additional capacitance between the gate electrode and the source/drain regions. As such, a method is needed that enables preventing electrical shorts of source/drain regions in FinFETs without compromising transistor packing density and performance of FinFETs.